Demand for semiconductors, wafers, integrated circuits and semiconductor devices (i.e., collectively “semiconductors”) continues to rapidly increase. With the continued market demand, there remain market pressures to increase the number of wafers that can be processed, reduce the geometries of finished wafers and their associated chip footprints, and increase component counts in the reduced geometries. Being able to sustain and meet the market demands with a reliable and consistent offering is a challenge however, in part because wafer manufacture is an environment that is both process sensitive and equipment intensive.
The fabrication of wafers (i.e., fabrication, fab, or fab environment) requires advanced processing equipment, unique toolings and extensive research efforts. Process tools (i.e., toolings) in these environments may often run in parallel or have multiple components to produce similar products (i.e., yields or outputs). Yet these same process tools, even when of the same manufacturer or source, may have unique variances in their individual performances which may create substantial or measurable differences in the quality of the products produced if unaccounted for.
A process tool may include a furnace, a furnace having a plurality of chambers, a furnace bank, a furnace tube, a processing chamber in which a wafer is acted upon, a processing activity point in a fab line where a wafer may be received or acted upon, and the like. In other aspects, a process tool may further include a controller or control mechanism for controlling a process tool and the tool's acts or actions with respect to the fab activity, in response to one or more commands, instruction sets, hardware or software commands, or other control-based directions of the controller.
As a result, in a traditional approach, it is often attempted to match the tool performance characteristics (TPCs), including machine characteristics, between process tools performing similar operations in one or more fab operations. With this approach, it is incorrectly believed that matched TPCs between similar process tools, even if identical in manufacturer and type, will result in identical or near-similar yields from each of the matched process tools. Unfortunately, even with matched process tools, yields are often subject to significant variance in what may otherwise appear to be an identical fab process.
An attempt to improve upon the traditional approach has also proven unfavorable where oxidation time of a particular process tool is adjusted in relation to the yield result so as to achieve a desired yield output and characteristic. Unfortunately, even with this attempted improvement, the traditional approach remains faulted as these time adjustments are limited to a single fab process for a single fab recipe on a particular process tool. This approach is not suited to accommodate typical fab production runs and foundry services having tens or hundreds of distinct processes being performed across tens or hundreds of process tools.
FIG. 1A depicts an example of a typical wafer 100 produced by a process tool in a process. In FIG. 1A, the wafer 100 has elements which may vary with respect to the type of process tooling and fab process undertaken in its manufacture, including a substrate 120 and a memory cell area 130. A memory cell often includes two or more field oxide areas (i.e., isolation regions) 110 which are often grown areas of oxide formed by a local oxidation of silicon (LOCOS) process.
The LOCOS process is in effect an isolation scheme commonly used in metal oxide semiconductors (MOS) and complementary MOS (CMOS) technology in which a thick pad of thermally grown SiO2 separates adjacent devices such as P-channel MOS and N-channel MOS transistors. Local oxidation is often accomplished by using silicon nitride to prevent oxidation of silicon in predetermined areas, and silicon is typically implanted between a silicon nitride region to form channel stops.
From FIG. 1A, the memory cell 130 is formed above an active area 140 of the substrate 120 and is situated typically between the adjacent field isolation regions 110. The memory cell 130 typically comprises a gate insulation layer 135 (i.e., tunnel oxide layer), a floating gate electrode 145 (often of polysilicon), a composite inter-poly insulation layer 150, and a control gate electrode 160 (often of polysilicon). In many implementations of the example of FIG. 1A, the insulation layer 150 is also known as an oxide-nitride-oxide (ONO) layer as it is often comprised of a layer of silicon dioxide 151, a layer of silicon nitride 152 and a layer of silicon dioxide 153, though other variations are also known.
From FIG. 1A, the thickness and dielectric constants of the floating gate electrode 135 and the layers of each of the ONO layer (i.e., 151, 152 and 153) may affect the overall performance of the memory cell and the associated integrated or electronic circuitry, depending on their thickness and formation details. Similarly there are also other characteristics of the memory cell related to physical structures, thickness, conductivity, uniformity, capacitance, band voltage, resistance, and growth impacts due to temperature and/or pressure during the deposition process, which may affect performance which directly results from a process tool's operation on the wafer (i.e., collectively “performance variables,” “performance variances” or “performance characteristics”).
Further, in the semiconductor fabrication field in particular, APC (advanced process control) may be employed in device manufacturing below 100 nm. The APC activities typically will need a stable thermal process, such as the one that significantly reduces wafer-to-wafer, batch-to-batch, and furnace-to-furnace differences, such that minimizing parameter variance is important when fabs process the same recipe, in multiple tools, for productivity and cycle time.
In a traditional furnace or furnace bank, there may exist more than one furnace tube in which a predetermined number of furnace tubes perform a similar process. FIG. 1B depicts a typical eight-tube furnace bank arrangement 190.
By example, the furnace bank of FIG. 1B is a process tool having two four-furnace banks at 191a and 191b, totaling eight similar separate tubes (i.e., furnace tubes) (191a, 191b, 191c, 191d, 191e, 191f, 191g, and 191h), each arranged to perform a furnace-based activity on a wafer set in the fab process. In a typical arrangement 190, each tube is arranged to receive a set of silicon wafers (192a, 192b, 192c, 192d, 192e, 192f, 192g, and 192h) which are typically received by the respective tube of the arrangement 190. In FIG. 1B, by example, wafer set 192h is about to be received into the proper bay area of furnace tube 191h, while all other wafer sets have been properly positioned in their respective tube bay. At 193a, 193b, 193c, 193d, 193e, 193f, 193g, and 193h are controllers each of which controls its respective furnace tube along 194a or 194b. A heat source is also an integral feature of a typical furnace (not shown). Once the wafers are inserted into the their respective tubes, the wafers are acted upon in accordance with the designated process, and thereafter removed. Once removed, yield variations of the wafers may be determined and compared.
Variances in the yield (e.g., produced semiconductor or memory cell) are often quantitatively determinable, even after attempting to traditionally match process tool or machine TPCs between similar process tools. Some of the yield variances can be determined quantitatively in the produced wafer's film thickness, stress, and dopant percentages, each of which is also directly associated with predictable comparative performances of the produced wafer.
With these traditional approaches, there are a number of limitations, however.
For instance, since yield variations and the associated results are uniquely dependent on at least both their respective process tools and specific fab recipes, in high capacity operations having substantial furnaces and recipe demands, significant numbers of recipes and/or equipment may need to be uniquely tailored and tuned for each process step. In such operations, even after these unique tunings are performed, further tunings may further be required in each tool every time there is even a minor adjustment needed to a tool, a recipe, or process.
In yet other instances, the traditional approaches are limited for furnace oxidation sequences where the oxidation time is varied for the same single recipe. With this approach, different oxidation times will yield oxides having different characteristics as each of the oxides in their respective tools are in effect growing at different rates and are therefore different. As a result time and temperature are not accurately controlled in the process sequence which is contrary to what is desired.
Therefore, optimally producing high-quality products in fab environment yielding consistency in produced wafers, fewer performance variances in process steps and reduced steps for recipe and process-specific tool variations, is desired. Additionally, limiting such performance variances commonly across a set of similar process tools, and in particular, improving consistency in yield output for similar-functioning but different process tools in a fab environment is also needed. Further, it is highly is desired to be able to match multiple differing line tools, such as furnaces, to develop consistency in process controls for oxide thickness control and particularly that of gate oxides.
The present invention in accordance with its various implementations herein, addresses such needs.